1. Field of the Invention
The present invention relates generally to a method and apparatus for designing the layout of a semiconductor circuit device. More particularly, this invention relates to a layout method and apparatus which shorten the time needed to design an LSI circuit pattern.
2. Description of the Related Art
To shorten the development period for large scale and highly integrated circuits, such as LSI circuits, it is essential to shorten the time required for designing the layout of such LSIs.
FIG. 1 presents a flowchart for a conventional layout process in the design of a semiconductor integrated circuit devices such as LSI and VLSI. In step S1, circuit design (logic design) is executed based on specifications to generate circuit connection data, or a net list 1. "The connection data" is defined as a compilation of information descriptive of primitives of a logic circuit, which includes a cell in a circuit and its interconnection elements. In step S2, the layout design of a mask pattern is performed using the circuit connection data 1 to generate layout data 2.
In step S3, parasitic elements included in an interconnection pattern are extracted based on the layout data 2 to generate parasitic element data 3. In step S4, a signal delay time originating from the parasitic elements is computed using the parasitic element data 3 to generate delay time data 4. In step S5, circuit logic simulation is performed using the data 1 to 4 to examine the signal delay time originating from the parasitic elements or to perform back annotation.
Steps S3 and S4 are batch processes for all the interconnection patterns included in the layout data 2. An increase in the number of interconnection patterns or increasing the integration scale of LSIs, lengthens the processing times in steps S3 and S4. That is, the time from the beginning of the circuit design process to the end of circuit logic simulation becomes longer.
When the circuit logic simulation shows that a desired operation cannot be performed due to a difference between signal propagation times, it is necessary to execute a circuit alteration routine to insert a buffer or layout correction to change the paths of the interconnection pattern in step S1 or S2. This layout correction necessitates repeating the processes in steps S3 and S4 and the circuit logic simulation. In other words, if layout correction is performed, the extraction of parasitic elements and the computation of the delay time should be executed. This increases the designing time.
To shorten the LSI design period, as shown in FIG. 2, a method for reducing the number of returns from the layout design to the circuit design has been proposed. In step S6, restriction data 5 is generated. This restriction data 5 includes data representing an allowable delay time in association with a plurality of critical signal lines and data representing allowable lengths of the critical signal lines based on the delay time. In step S7, using the circuit connection data 1, a plurality of cells are automatically positioned in such a way as to meet the restriction data 5 to generate positioning data 6. In step S8, automatic interconnection is performed based on the positioning data 6 to generate layout data 2.
Even if the layout data 2 satisfies the restriction data 5 generated in steps S7 and S8, the LSI as a whole may still have some problems depending on, for example, the states of the interconnection paths. To cope with such a problems, an operator executes interactive layout correction in step S9 to change the positions of the cells and the routing of the interconnections. As a result, new layout data 2a is generated. Based on this new layout data 2a, the parasitic element data 3 and the delay time 4 are generated as shown in FIG. 1, step S3. Then, circuit logic simulation is performed in step S5.
The restriction data 5 defines restrictions for the automatic positioning of the elements in the automatic positioning/interconnecting process. The restriction data 5 is not however associated with the layout data 2 and 2a. It is not therefore possible to guarantee that the new layout data 2a meets the conditions of the restriction data 5. To check if the restriction conditions are met, processes in steps S3 to S5 are needed. If the results of the circuit logic simulation, step S5, show that the restriction conditions are not met and there is a signal timing problem, the flow should return to step S9 to allow the operator to correct the layout. This requires a significant time from the start of circuit design to the end thereof, thus resulting in a longer period until the completion of LSI development.